1. Field of the Invention
The present invention generally relates to a method for forming a semiconductor device, and more particularly to a method for forming a hybrid low-k film stack to avoid the thermal stress effect.
2. Description of the Prior Art
It is the nature of semiconductor physics that as the feature sizes are scaled down, the performance of internal devices, such as device speed, as well as the functional capability improves. The overall circuit speed, however, becomes more dependent upon the propagation speed of the signals along the interconnects that connect the various devices together. With the advent of very and ultra large scale integration (VLSI and ULSI) circuits, it has therefore become even more important that the metal conductors that form the interconnections between devices as well as between circuits in a semiconductor have low resistivity for high signal propagation. Copper is often preferred for its low resistivity, as well as for resistance to electromigration and stress voiding properties.
In the manufacture of devices on a semiconductor wafer, it is now the practice to fabricate multiple levels of conductive (typically metal) layers above a substrate. The multiple metallization layers are employed in order to accommodate higher densities as device dimensions shrink well below one micron design rules. Likewise, the size of interconnect structures will also need to be shrunk, in order to accommodate the smaller dimensions. Thus, as integrated circuit technology advances into the sub-0.25 micron range, more advanced interconnect architecture and new materials are required.
Low dielectric constant materials have the advantage that higher performance IC devices may be manufactured with minimal increases in chip size. The reduced capacitance given by these materials permits shrinking spacing between metal lines to below 0.25 xcexcm and the ability to decease the number of levels of metal in a device. The technologies being considered for low-k applications are CVD or spin-on of inorganic or organic polymeric materials. More recent advances in Sixe2x80x94O based polymer chemistry have seen the development of new materials that have k=2.5-3.0 by changing the structure of the polymer.
Low-k material is popularly used to improve integrated circuit performance of RC delay below 0.18 micron technology. However, thermal stress effect impacts severely on these low-k materials, especially on organic spin-on material, for instance SiLK. On the other hand, chemical vapor deposition low-k materials have better thermal conduction than organic spin-on materials. Therefore, the inevitable combination of these two materials beyond 0.13 generation is the most critical point in semiconductor processes.
For the foregoing reasons, there is a necessary for a method for forming a hybrid low-k film stack to avoid the thermal stress effect to reduce the thermal stress effect issue.
In accordance with the present invention, a method is provided for forming a hybrid low-k film stack to avoid the thermal stress effect that substantially can be used to decrease thermal stress in a conventional process.
One object of the present invention is to provide a method for forming a hybrid low-k film stack to avoid the thermal stress effect to apply below 0.13 micron process.
Another object of the present invention is to provide a method for forming hybrid low-k film stack to avoid thermal stress effect to apply below 0.13 micron process.
In order to achieve the above objects, the present invention provides a method for forming a hybrid low-k film stack, in which an organic spin-on low-k material and CVD low-k material are combined to avoid the thermal stress effect. This invention also provides a method for applying a hybrid low-k film stack to a dual damascene process.